Repurposing existing HDL tools to help writing better code

A JSON library implemented in VHDL.

Portable HyperRAM controller

Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀

High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model

Connect to your VHDL simulation via JTAG! GDB <-TCP-> OpenOCD <-remote bitbang-> cosim_jtag <-VHPI or FLI-> VHDL simulator.

Modelsim QEMU Unicorn integration via the FLI

This project is focused on the design and verification of digital logic circuits, particularly targeting chip design using Verilog, SystemVerilog, and SVA. The main objectives included designing modules compliant with industry standards such as APB (Advanced Peripheral Bus), memory systems, and systolic matrix multiplication.

Utilities for Avalon Memory Map

Getting started with SystemVerilog: Hardware Description Language for design and verification.

A Python-based IP Core Management Infrastructure.

This project implements a SPI (Serial Peripheral Interface) slave module with a single port RAM block. The SPI slave module receives data from a master device and communicates with the single port RAM to store and retrieve data.

Simulation and implementation flow for hardware description languages

SublimeLinter plugin for linting Verilog and SystemVerilog with Modelsim vlog

Collection of scripts for EDA tools

In-Memory Accelerator Controller

Configurable AXI4 Verification IP developed using UVM, featuring reusable master and slave agents, protocol checking, functional coverage, and scoreboard-based verification.

A wrapper for colorizing the output of Mentor Graphics QuestaSim messages.

This repository contains the digital design and verification of the AMBA3 (Advanced Microcontroller Bus Architecture) and AMBA4 APB (Advanced Peripheral Bus) protocols.